With high speed (e.g., several Gigabits per second) data receivers of this type, a received data signal is typically sampled with a clock signal, which has a frequency of the value of half the data rate of the data signal, in order in this way to create two data signals with half the data rate. This process is repeated in several steps, the data rate of the data signals being halved at each step. To achieve this, in each step clock signals with a corresponding clock frequency are required, which are likewise halved at every step.
Conventionally, these clock signals are generated by a central clock frequency divider. The consequence of this is that the clock signals need to be conveyed over broad paths to scanning units of the different steps, which at high speeds is difficult and leads to a circuit structure which is not entirely symmetrical, which can lead to imprecisions in the sampling of the data.
In addition to this, when demultiplexing the data, (i.e., when sampling the data with the individual clock signal in each case) output data signals are frequently generated which are displaced mutually by half a bit length. This displacement must be compensated for, for example by temporary storage during half a clock pulse cycle, in order nevertheless for a central clock signal generation to be used. In this situation, however, in practice an additional problem frequently arises in that the temporarily-stored data can be more strongly amplified in relation to the other data, which incurs undesirable dependencies of a bit failure rate and a clock recovery from a position of a bit in the data flow which is received in each case. In addition to this, temporary storage of this kind can also be difficult, depending on the circuit technology used.
Another formulation consists of using what is referred to as a distributed frequency divider structure, i.e., of dividing the clock pulses down parallel to the sampling devices. However, in view of the fact that, with the frequency dividers which are normally used, the initial state is determined at random, in this situation what is referred to as reset synchronization is required, in order for all the frequency dividers to start in a defined state. A reset synchronization of this kind is, however, very difficult to achieve at high speeds.
If, in addition to this, what is referred to as a half-rate arrangement with a quadrature oscillator is pursued, in which the oscillator runs at half the clock frequency of the data rate, and the four phases of the quadrature oscillator produced are used to sample the data signal, then as early as in the first step several frequency dividers must be used in parallel to divide down the individual clock phases of the oscillator. With a quadrature oscillator these clock phases are displaced mutually by a quarter pulse. This slight displacement, and the need for several frequency dividers which must start in the same start state, make reset synchronisation with a distributed structure practically impossible. Accordingly, a distributed frequency divider structure is normally not used at high speeds.